Doubts with cycle and phasor

[MBM]

Hello, there is one thing I don´t understand. At page number 238 you say that it´s the same to connect a phasor with argument 440 to right inlet of a cycle, that make a cycle with argument 440. But if you make this patch:

----------begin_max5_patcher----------
595.3ocyW9saaBCEF+Z3o.4aWVDXr4O6t8bTUM4.tIdBrQfiRZqZd1G1.IYc
sIFFX0aLhCFym+4y2wlWcc.aDGoM.ue38fmiyqtNN5Pp.N826.JIGyJHM5tA
dpPv2WBV08nmDbYC6Ep5QAv098ga6gXurfJ0uCrOZWH4yUztOnZrHRvJOvFB
eKv6w99UQjY6X7s+pllI65Z.Ntcva+DH0ErupE11d9cTBgSJ0iL3m0LRwfDY
45XhM+96XH3h.Y7A8Enh8lqqpYkgXfSOzNhCCmjdTKTP6DJuj1z34uFOJFE7
YLxDrDiUsIvoQETxRSkucZdXQCaKucJbKh.80r.FoSQBgqwSBIweHRfyGRxd
NqfdxCg7sFZF7PIopKQISLaIZoQyYOzrAmahkPnNiA04gvSjJ34yCsubCsdd
Jvx3lUdsmAII+OUWQnktNR0NRin1dES5wR.T6XvnIxE3r4XT1BxV5+.lFonx
BVkjthpo55HggcUSFKNRs.MH0xCLdt3fMfhNsHraCmXzzfxhueSNIab9F+ar
QRp9jFnPssHLdhGFa1lxaIL9Iv3pL169W0Ui7laalpqJF5qWfizS8zzqlsWa
0sywFrcAPnexksHG+Jcvcohd7.EL96+WDslTw+aT0H1WmMLO5+DdWTUNsQx3
DISvupOpC04EbtS6X44T90o5kr7JQa5PuF7d7CW2LURpe139ZJxpZRcT+6po
2I7EWSwlvI6JoHSSmrnlLIcJvtYSXSvjkW5PlnI6lgmZhoypJJ9KmhPFpnfu
bJZpLp8l2b+CYX4dDA
-----------end_max5_patcher-----------

You can see that they not cancel as they would do if they would be the same. What am I missing?

And I don´t understand why if you give a frecuency (let´s say 440) to a cycle object and in its right inlet you give it a phasor with 220 (for example), you obtain a frecuency of 660. I mean: why they sum?

Actually I don´t understand exactly the concept of "phasor" when you connect it to the right inlet of cycle. I can´t imagine it "physically".

Thank you in advance and best regards.

[Maurizio Giri]

Hi, you discovered a bug (or issue), the two frequencies should be the same (in antiphase) but they aren't!
This is probably due to a slightly different internal calculation for the frequency in the two objects (cycle~ and phasor~): I'll tell this to cycling 74.

Re: your second question, you should imagine that cycle~ has an "internal phasor~" which reads a sinus table as it goes from 0 to 1 (just like the wave~ object presented at page 248, only the phasor~ is not outside, but inside the object).
When you sent a 0.5 in the right inlet of the cycle~ object in your patch, you added that value to the internal phase of the oscillator, right? The starting phase of cycle~ was at 0, and now is at 0.5. If you send a phasor~ signal in the right inlet of cycle~ you are adding the phasor~ signal to the internal phase of the oscillator.
So, if the cycle~ frequency is 440 Hz and, for instance, the external phasor~ frequency is also 440 Hz, we have this situation:

time        internal phase      external phasor~     resulting phase
n0           0.0                     0.0                         0.0
n1           0.1                     0.1                         0.2
n2           0.2                     0.2                         0.4
n3           0.3                     0.3                         0.6
n4           0.4                     0.4                         0.8

etc.

so the resulting phase is twice as fast, i.e. the frequency is 880 Hz: the two frequencies are summed.

m

[MBM]

Ok, thank you very much, now I understand it and I´m much more relaxed ;-) Also for me it´s a relief that my problem with cycle and phasor was a bug or issue, because I has been all the day thinking what was I missing...

Thank you very much for your quick and effective answer, it´s as good as your book.

Best regards.

[MBM]

(And apologize for my very bad english :-) )

[MBM]

There is something I don´t understand yet... Let´s see: if you connect a phasor to the right inlet of a cycle that has not argument (so its phase is always 1), would not you to have another saw wave? Because their sum it´s always the phase of phasor plus 1... Sorry, maybe it´s a stupid question, but I can´t see it...

Thanks and best regards.

[Maurizio Giri]

If the cycle~ has no arguments, its phase is at 0 (i.e. at the beginning: phase goes ftom 0 to 1).
As I said in my previous post the cycle~ object has an internal table with a sinus waveform stored. When the phase is at 0, cycle~ reads the beginning of its table, when it is at 0.5 it reads the middle of the table, when it is at 1 it reads the end of the table, etc.
So, sending a ramp from 0 to 1 with a phasor~ connected to the right inlet of cycle~ makes cycle~ to "spit out" a sine wavecycle (i.e. the content of its table).

m

[MBM]

Ok, now I understand everything, the problem was in my english reading (it´s long to explain where was my mistake). But now everything it´s clear. Thank you for your patience.

Best regards.